1. Field of the Invention
The present invention relates to an offset compensation circuit. More particularly, the present invention relates to an image sensor and offset-able reference voltage generator.
2. Description of Related Art
In recent years, more and more electronic products such as mobile phones, personal digital assistant and toys incorporate a built-in camera. To meet various personal requirements, especially portability of the mobile devices, image sensors with low power consumption and high picture quality are in great demand. FIG. 1A is a block diagram of a conventional image sensor. As shown in FIG. 1A, the image sensor comprises an array of pixels 110, a row driver/voltage generator 120, a sample and hold circuit 130, a signal gain amplifier 140 and an analog/digital (A/D) converter 150. The row driver/voltage generator 120 provides row-driving signals 121 to the pixel array 110, reference voltages 122 to the analog/digital converter 150 and the signal gain amplifier 140 and reference voltage VCL to the sample and hold pixel circuit 130. Each row electrode (not shown) of the pixel array 110 receives a corresponding row-driving signal 121. After sensing the image, the pixel array outputs the pixel signals 111 of various columns according to the timing of the column-driving signal 121. In the meantime, the pixel sample/hold circuit 130 samples and holds the pixel signals 111 from various columns. Thereafter, various sample/hold pixel signals are output in sequence as a cascade of pixel signals 131. The signal gain amplifier 140 amplifies the received pixel signals 131 to generate pixel signals 141. Typically, the analog/digital converter 150 is a pipeline A/D converter. The A/D converter 150 converts the analog pixel signals 141 into digital pixel signals 151 according to the reference voltage 122 ready for subsequent circuit processing and manipulation (only represented by a single control logic circuit 160).
In the image sensor read-out circuit, the process of generating analog reference voltage consumes the most power. In the following, the sample/hold circuit 130 inside a complementary metal-oxide-semiconductor (CMOS) image sensor is used as an example. FIG. 1B is a conventional sample/hold circuit for a CMOS image sensor. To simplify the following discussion, various pixels within the pixel array 110 are represented by a single pixel 112. In addition, only one set of the sample/hold circuits within the pixel sample/hold circuit 130 is shown. In general, the CMOS image sensor needs to sample pixel signal voltage and pixel reset voltage. During the sampling process, a reference voltage VCL is required. To sample the pixel signal voltage, the inductor-controlled switches clamp and samp_sig are closed while the inductor-controlled switches samp_rst, cb and col_addr are opened. Thus, the differential voltage between the pixel signal voltage and the reference voltage VCL is registered by a capacitor CS1. To sample the pixel reset voltage, the inductor-controlled switches clamp and samp_rst are closed while the inductor-controlled switches samp_sig, cb and col_addr are opened. Thus, the voltage differential between the pixel reset voltage and the reference voltage VCL is registered by a capacitor CS2. After sampling, the inductor-controlled switches clamp, samp_sig and samp_rst are opened. Thereafter, the inductor-controlled switch cb is closed to initiate a hold period. During the hold period, the pixel signals 111 in various columns are held in a corresponding sample/hold circuit. The sampled data inside various sample/hold circuits are output as pixel signals 131 in a cascade to the signal gain amplifier 140 by closing the inductor-controlled switch col_addr sequentially.
In practice, because of the leakage in some of the pixel photo-diodes inside the pixel array 110, the sampled pixel reset voltage is highly inaccurate. On the other hand, factors such as production offset, circuit loading and layout area of sampling capacitor often lead to a fixed pattern noise on the display screen between vertical columns. To combat this problem, a conventional technique is to install an offset-correcting circuit 170 in each sample/hold circuit within the pixel sample circuit 130. FIG. 1C shows the timing of the signals in FIG. 1B. During the signal-sampling period, the inductor-controlled switch clamp is conductive (a high voltage potential in the timing diagram indicates a conductive state for the inductor-controlled switch and an open state vice versa). Furthermore, the offset-correcting circuit 170 selects to output the voltage at point B (for example, the reference voltage VCL). Since the sampling of the pixel signal voltage and the pixel reset voltage has been described before, details are not repeated here. To correct the offset in the pixel signal, the offset-correcting circuit 170 needs to switch from connection with point B to point A after opening up the inductor-controlled switch samp_rst (at time C) but before closing the inductor-controlled switch clamp (at time D). In other words, the offset-correction circuit 170 needs to change from outputting the reference voltage VCL to the offset voltage Voffset within the time interval between time C and D. Consequently, the terminals of an offset-compensating capacitor 171 have a voltage Voffset-VCL so that the pixel signal has an offset voltage of Voffset-VCL.
Typically, the sample/hold circuits corresponding to each column of pixels must have a group of offset-correcting circuits. With the growing size of a pixel array, the number of sample/hold circuits is increased and hence more offset-correcting circuits (each offset-correcting circuit at least comprises an offset-compensating capacitor and an operational amplifier) are required. In other words, the required chip area increases (an increase in production cost) as the number of pixels is increased. In addition, to meet the timing specification, the driving capacity of the operational amplifier inside the offset-correcting circuit for driving the capacitor must be increased along with the increase in the number of pixels. Therefore, power rating of the operational amplifier is increased as well. Furthermore, there may be a mismatch between the capacitor and parasitic capacitor inside each sample/hold circuit due to production offset leading to the formation of a corresponding fixed pattern noise between each column of image pixels.